The present invention relates to network input/output (I/O) devices, such as a serial input/output device.
A block diagram showing the structure of a conventional I/O device is shown in FIG. 3. The I/O device is comprised of transmission register 3, reception register 4, transmission first-in/first-out (FIFO) register 5a, reception FIFO 5b, and data bus 8. FIFOs 5a and 5b are first-in/first-out shift registers, and each data bus 8 is connected to a host computer not shown in FIG. 3. At present, when data are transmitted from the host computer through a network to the outside the host computer writes data to an assigned address within transmission FIFO 5a and the data are stored in a memory within FIFO 5a from data bus 8. If more data are written to the same address, the previously stored data are shifted to an output port, and data are successively stored. Data can thus be stored to the maximum limit allowed by the structure of FIFO 5a. When transmission register 3 is enabled for transmission, transmission FIFO 5a transfers data to transmission register 3 one byte at a time in the order of storage, and transmission register 3 serially outputs data 7a to network N. When transmission of one byte of data is completed, transmission FIFO 5a sends the next byte of data to transmission register 3. In the reception of data, reception register 4 receives data 7b from network N serially. When one byte of data is received, reception register 4 transfers the reception data to reception FIFO 5b, then begins receiving the next data. When the address assigned in reception FIFO 5b is read, reception FIFO 5b outputs the data to data bus 8 in order of storage, starting with the earliest data.
FIG. 4 shows plural serial I/Os connected to network N in a connection pattern for clock-synchronized operations, while FIG. 5 shows the operation. The serial output terminal 11a, serial input terminal 12a, and clock terminal 13a of serial I/O 10a are connected respectively through a network to serial input terminal 12b, serial output terminal 12a, and clock terminal 13b of serial I/O 10b. The transfer clock is generated by either serial I/O 10a or serial I/O 10b, with both using the same transfer clock. As shown in FIG. 5, transfer register 3 shifts and outputs data 7a to serial output terminal 11a with each fall of transfer clock .0.. On the reception side, reception register 4 shifts and latches data 7b from input terminal 12a with each rise of transfer clock .0..
FIG. 6 shows plural serial I/Os connected to network N in a connection pattern for asynchronous universal asynchronous receiver/transmitter (UART) operations, while FIG. 7 shows the operation. The connection of serial input terminals 11a and 11b and serial output terminals 12a and 12b is the same as that for clock-synchronized operations, but without the connection of clock terminals 13a and 13b. Moreover, start bit, stop bit, parity bit, transfer speed, and other transmission specifications are the same for both serial I/O 10a and serial I/O 10b. Transmission register 3 shifts and outputs data 7 to serial output terminal 11a at the fall of internally generated transmission clock .0. 1. On the reception side, reception register 4 shifts and latches data 7b in synchronization with the receipt of start bit ST at the rise of internally generated clock .0. 2.
As described above, when the same transfer clock .0. is used by transmission register 3 and reception register 4 in the clock-synchronized operations shown in FIG. 4, transmission and reception occur in synchronization. On the other hand, when transmission register 3 uses transmission clock .0. 1 and reception register 4 uses reception clock .0. 2 in the UART configuration shown in FIG. 6, transmission and reception occur asynchronously.
Due to the structure of a conventional I/O device as described above, the use of a UART configuration in which transmission and reception occur asynchronously results in the need for transmission register 3 and reception register 4 to incorporate transmission FIFO 5a and reception FIFO 5b, respectively. In the construction of a system, reception data are read and used with high frequency each time one byte of data is received on the reception side, resulting in the inefficient use of the reception FIFO. When clock synchronization is used, transmission data are written to the transmission FIFO, and reception data are read from the reception FIFO. FIG. 8 is block diagram for another serial I/O using clock synchronization, in which transmission data are written to FIFO 5 and transferred to transfer register 3 in one-byte units at the start of transmission. At this time, the empty space created in FIFO 5 by the transfer and reading of the first byte is used to store data received from the network by reception register 4. However, since the asynchronous serial I/O configuration of FIG. 4 uses two times as many FIFOs as the serial I/O using clock synchronization of FIG. 8, it results in a large pattern area and the inefficient use of substrate area.